Realizing vertical bipolar transistors in a standard CMOS technology for the design of low-cost BiCMOS integrated circuits.
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Realizing vertical bipolar transistors in a standard CMOS technology for the design of low-cost BiCMOS integrated circuits.

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Published .
Written in English


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About the Edition

This thesis describes the realization of isolated vertical npn transistors in generic CMOS technologies. An improved layout for these parasitic transistors is proposed. The electrical characteristics and modelling of the proposed device are presented. The design, realization, and fabrication of a high-speed open-loop preamplifier using these bipolar transistors are also presented. The preamplifier was found to have more than a 1 GHz bandwidth as well as less than -35 dB THD, as was verified using die-probe measurements. The amplifier achieved 10.4 dB gain and a 0 dBm IIP3. The collector-base and the collector-emitter breakdown voltages are 14.8V and 9V, respectively. The output impedance and noise characteristics are comparatively good. The measured current gains, on the order of 20, are less than what would be preferred, but not excessively so, and the unity-gain frequencies on the order of 4 GHz, are much less than would be the case for a vertical npn in a typical BiCMOS process, but still are adequate for many applications.

The Physical Object
Pagination110 p.
Number of Pages110
ID Numbers
Open LibraryOL19512560M
ISBN 100612953637

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